1. Field of the Invention
The present invention relates to a computer processing. More particularly, the present invention relates to a processing in which processes are performed by a reconfigurable logic circuit.
2. Description of the Related Art
In recent years, the communication speed of computer networks has been enhanced. The performance of the processor is a bottleneck for the speed up of the network. For solving the bottleneck problem, the technique for speeding up processing by offloading the processing of coding or protocol stack which is conventionally performed in processor is known. For example, in encoding and decoding processing, a method is disclosed in the following online content: “Product Lineup—64-Bit VR Series”, NEC Electronics Corporation, of Jul. 28, 2005.
In this method, an encoding-decoding dedicated hardware is connected to a bus of a processor and the dedicated hardware is called in the encoding-decoding processing in software processing. Also, a method in which a circuit dedicated for encoding and decoding processing is incorporated in a processor is disclosed in the following online content:
“AES Cipher Engine”, Techno Create, of Jul. 28, 2005.
However, the functions which are processed by the hardware block offloaded from central processing unit for achieving higher speed are fixed and cannot be changed. As a result, the variety of processes whose speeds can be made faster in the hardware is limited so that the application to the variety of processes is restricted. Also, there is a case that the kinds of the processes whose speed is desired to be made faster is different depending on the kind of data inputted to the processor. In that case, the effect cannot be achieved enough in the hardware performing a fixed function, so that the speed of the process is not necessarily improved.
For solving these problems, the dynamically reconfigurable circuit is known which changes the offloaded hardware circuit during the processing and executes the wide variety of processes.
As a publicly known technique, Japanese Laid Open Patent Application (JP-P 2003-208305A) discloses a data processing device that reduces the influence of the time required for the dynamic circuit restructuring on the processing performance.
In the data processing device disclosed in the patent document 1, in the data processing, in parallel to a process that is carried out on CPU and using a first memory and a third memory, a controlling unit carries out a process for structuring a reconfigurable logic circuit in accordance with a content of a restructuring information memory. Then, after finishing the structuring of the reconfigurable logic circuit, instead of the CPU, the reconfigurable logic circuit carries out a process by using the second memory and the third memory.
However, the storage region for storing the information used in restructuring the circuits is limited. When there are a large variety of processes that are desired to be executed through the restructured hardware, it is necessary to enhance the restructuring information memory or use an external memory for holding the restructuring information (configuration data) necessary for restructuring. In the case that the restructuring information memory is enhanced, a circuit area becomes larger and the cost is increased. Also, in the case that the external memory is used for storing the configuration data used for restructuring, it takes a time to transfer the configuration data, and the process time becomes long, which results in the drop in the process performance.
Further conventional techniques are described below. Japanese Laid Open Patent Application (JP-P 2001-067212A) discloses a trouble avoidance information processing system which transfers structure information and a micro command in an external storage device to a main storage device when an information processing system is started and then executes a starting process in accordance with the structure information.
Japanese Laid Open Patent Application (JP-A-Heisei, 4-042342) discloses a bus arbitration circuit which holds bus use request signals form data transfer modules and determines the priorities of the bus use requests from the data transfer modules and permits the use in accordance with the priorities.
Japanese Laid Open Patent Application (JP-A-Heisei, 11-085608) discloses a computer system which divides memory into several groups and gives priorities to assign the memories to the respective groups and then assigns an area in order from the group having a higher priority in response to the assignment request of the memory.